Tensorflow for HPC

Google has developed TensorFlow, a truly complete platform for ML. TensorFlow has many ingredients, for example:

• many domain specific libraries for machine learning

• the TensorFlow domain specific data-flow language

• carefully organized input and output for data flow

• an optimizing runtime and compiler

• hardware implementations of TensorFlow operations in TensorFlow processing unit (TPU) chips

The performance of the platform is amazing, and it begs the question if it will be useful for HPC in a similar manner that GPU’s heralded a revolution.

InsideHPC created a podcast based on my lecture about this at the South African National HPC Conference CHPC 2018 Conference in Cape Town.

The slides are here and here

AI Cern SKA Workshop

In September 2018 we had a wonderful workshop at the Alan Turing Institute in London concerning AI at CERN and SKA.

There were many wonderful presentations ranging from applications of AI to particle discovery at CERN, to deep mathematics concerning information extraction and very novel applications of ML to cast a dramatically new light on numerical solutions to physics PDE’s - in this case for structure formation in the early Universe.

The presentations can be found on the Indico site, no video recordings were made.

Performance Engineering for the SKA Telescope

PERFORMANCE ENGINEERING FOR THE SKA TELESCOPE

I gave a keynote at ICPE 2018 in Berlin about performance aspects in computing for the SKA telescope. The slides were posted here and the local copy is here.

ABSTRACT

The SKA radio telescope will be a massive world class scientific instrument, currently under design by a world wide consortium, to progress to full operation in South Africa and Australia in the mid 2020’s. The capabilities of the telescope are expected to enable major scientific breakthroughs. At the center of its data processing sits the Science Data Processor, a large HPC system with specialized software. In this lecture we will give a high level overview of the project and progress to the computing and data related architecture. Then we will discuss the work of the SDP design consortium to understand and achieve the many performance requirements leveraging hardware and algorithms. Among these is a requirement for memory bandwidth exceeding 100 PB/sec.